1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly, to a non-volatile memory cell capable of suppressing a leakage current caused by over-erasure and a method for fabricating the same.
2. Discussion of the Related Art
In general, there are two different structures in a conventional flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cell of the non-volatile memory cell: an Eprom (Erasable and Programmable Read Only Memory) Tunnel Oxide (ETOX) structure and a split-gate structure.
Referring to FIG. 1, as a first example of the conventional flash EEPROM, the ETOX structure includes a semiconductor substrate 1, a floating gate insulating film 2 formed on the semiconductor substrate 1, a floating gate 3 formed on the floating gate insulating film 2, a control gate insulating film 4 formed on the floating gate 3, a control gate 5 formed on the control gate insulating film 4, and source 6 and drain 7 formed in the semiconductor substrate 1 at both sides of the control gate 5.
The operations of the conventional flash EEPROM having the aforementioned system will now be described.
During the writing operation, a source 6 of a control transistor (not shown) as a memory cell is grounded, and a control gate 5 and a drain 7 are applied with voltages of 12 V and 7 V, respectively. Then, hot carriers in the channel region are charged in the floating gate 3 to store data. During the erasing operation, the source 6 is applied with 12 V, or the control gate 5 is applied with a negative voltage, to erase the charges in the floating gate 3 while keeping the control gate 5 grounded and the drain 7 opened.
However, in the conventional ETOX type flash EEPROM cell, if the data is erased excessively, a leakage current may flow in the cell. The leakage current is caused by the formation of a floating gate channel coming from the positive charges presenting in the floating gate and the easy migration of the electrons generated in a depletion region adjacent to the source toward the drain. To cope with this problem, the split-gate type flash memory cell has been suggested to suppress the leakage current between the source and the drain.
As a second example, the conventional split-gate type flash EEPROM cell is now described. FIG. 2 illustrates a cross section of the conventional non-volatile memory cell(i.e., the EEPROM).
Referring to FIG. 2, the conventional split-gate type flash EEPROM cell includes a semiconductor substrate 11, a floating gate insulating film 12 formed on the semiconductor substrate 11, a floating gate 13 formed on the floating gate insulating film 12, a control gate insulating film 14 formed on the floating gate insulating film 12 and the floating gate 13, a control gate 15 formed on the control gate insulating film 14, and source 16 and drain 17 formed in the semiconductor substrate on one side of the control gate 15 and one side of the floating gate 13, respectively.
The operations of writing to and reading from the conventional split-gate type flash memory cell are the same as the conventional ETOX type flash memory cell.
Since a channel length of a selecting gate of the conventional split-gate type flash memory cell is longer than that of the conventional ETOX type flash memory cell, the charges in the floating gate suppress the leakage current between the source and drain during an over-erasure. In order to provide a higher packing density in the conventional split-gate type flash memory cells of a non-volatile memory device, a shorter channel length of a selecting gate is desirable. However, the shorter channel length causes an increase of the leakage current due to the punch-through between the drain and the source. Therefore, the higher the packing density of the EEPROM, the shorter the channel length of the selection gate in the conventional flash EEPROM cell. This results in forming a floating gate channel due to the positive charges present in the floating gate 13, as shown in FIG. 3. In addition, the shorter channel length increases the leakage current by causing an easy migration of the electrons either diffused from the source 16 or generated in the depletion region adjacent to the source 16 toward the drain 17. Moreover, since the coplanar formation of the selection transistor and the control transistor in the conventional flash EEPROM increases an occupied area of the transistor, the structure of the conventional flash EEPROM cell is not suitable for fabrication of highly packed devices.